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////  PicoDefines.v                                               ////
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////                                                              ////
////  This file is part of the "Pico E12" project                 ////
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//// Copyright (C) 2005, Pico Computing, INC.                     ////
//// http://www.picocomputing.com                                 ////
////                                                              ////
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`ifndef VERSION

//-----------------------Version 4.2.0.0 ----------------------------------
`define VERSION_MAJOR                8'h04
`define VERSION_MINOR                8'h02
`define VERSION_RELEASE              8'h00
`ifndef VERSION_COUNTER	                  
 `define VERSION_COUNTER             8'h00
`endif
`define VERSION_UPPER_UPPER         `VERSION_MAJOR
`define VERSION_UPPER_LOWER         `VERSION_MINOR
`define VERSION_LOWER_UPPER         `VERSION_RELEASE
`define VERSION_LOWER_LOWER         `VERSION_COUNTER

//Card Selection
`ifndef IS_LX25                                                     /*Define this for an LX25 FPGA*/
   `ifndef IS_FX12                                                  /*Define this for an FX12 FPGA*/
      Error missing IS_LX25 or IS_FX12
   `endif
`endif

`define VERSION CF RELEASE FEBRUARY 25, 2006

// Enable implied options
`define ENABLE_TURBOLOADER          //Always enabled
//`define ENABLE_MDIO - JBC - we do not always want this enabled

`ifdef ENABLE_PPC
   `define ENABLE_CPU
   `define ENABLE_KEYHOLE
`else
   `undef ENABLE_KEYHOLE
`endif
`ifdef ENABLE_PPC
   `define ENABLE_RAM_PADS
   `define ENABLE_GPIO_PADS // JBC - 2/22/07 this was originally commented out, but we need these pads
							// enabled in order for RS-232 to work, and we do not want to ENABLE_GPIO for RS232 
`endif
`ifdef ENABLE_GPIO
   `define ENABLE_GPIO_PADS
`endif

//BACKPLANE_REQUIRED compels the tristates outside the FPGA to operate in a mode that is compatible with
//the Little Brother board. It should be defined as 1 in this case. In all other cases when the image is expected
//to operate in a hosted mode and/or a backplane mode it should be defined as 0.
`ifndef BACKPLANE_REQUIRED
	`define BACKPLANE_REQUIRED 0
`endif
 
//-----------------------Optional Peripherals----------------------------
//`define DISABLE_TUPLE                                              /*This enables the configuration ROM (also known as a tuple)*/
`define ENABLE_CARD_INFO                                             /*This enables a module that holds the firmware version number and capabilities*/
//`define ENABLE_GPIO                                                /*General Purpose IO Interfaces*/

//--------------------------------- Card Capabilities
// Capability definitions used to tell software what the fpga capabilities have been synthesized.
// To indicate the capabilities an image has, define IMAGE_CAPABILITIES in PicoDefines.v.
//   For example: `define IMAGE_CAPABILITIES (`PICO_CAP_FLASH | `PICO_CAP_TURBOLOADER)
`define PICO_CAP_FLASH              16'h0001             //Can access flash ROM from PC side (aways available).
`ifdef ENABLE_TURBOLOADER
   `define PICO_CAP_TURBOLOADER     16'h0002             //Has access to TurboLoader.
`endif

`ifdef ENABLE_KEYHOLE
   `define PICO_CAP_KEYHOLE         16'h0004             //Supports keyhole.
`else 
   `define PICO_CAP_KEYHOLE         16'h0000             //Does not support keyhole.
`endif

`define PICO_CAP_BUSMASTERING       16'h0000             //Image does not have bus mastering

`ifdef ENABLE_ADC
   `define PICO_CAP_ADC             16'h0020             //Image has A/D (same bit!)
`else   
`ifdef ENABLE_DAC 
   `define PICO_CAP_ADC             16'h0020             //Image has D/A (same bit!)
`else 
   `define PICO_CAP_ADC             16'h0000             //Image does not have A/D or D/A
`endif
`endif

`ifdef ENABLE_PIC
   `define PICO_CAP_PIC             16'h0040             //Image has PIC access
`else 
   `define PICO_CAP_PIC             16'h0000             //Image does not have PIC access
`endif

`ifdef ENABLE_JTAG_SPY
   `define PICO_CAP_JTAG_SPY        16'h0080             //Image will capture JTAG access through LPT port
`else 
   `define PICO_CAP_JTAG_SPY        16'h0000             //Image does not have JTAG capture
`endif

`ifdef ENABLE_ETH
   `define PICO_CAP_ETHERNET        16'h0100             //Image has ethernet capability
`else 
   `define PICO_CAP_ETHERNET        16'h0000             //Image does not have Ethernet capability
`endif

`ifdef ENABLE_PPC
   `define PICO_CAP_UARTLITE        16'h0200             //Image has uartlite port
`else
   `define PICO_CAP_UARTLITE        16'h0000
`endif

`define IMAGE_CAPABILITIES  (`PICO_CAP_FLASH | `PICO_CAP_TURBOLOADER | `PICO_CAP_KEYHOLE | `PICO_CAP_BUSMASTERING | `PICO_CAP_ADC | `PICO_CAP_PIC | `PICO_CAP_JTAG_SPY | `PICO_CAP_ETHERNET| `PICO_CAP_UARTLITE)

//Bits of Capabilities register read by PPC.
`define PICO_STANDALONE_SW          32'h00008000         //

//-----------------------------Ethernet----------------------------------
`define MDIO_ADDRESS 26'h200000                       /*0x08000000*/ /*Ethernet Management Interface*/


//---------------------System Generator for DSP--------------------------
`define SYSGEN_BANK_ADDRESS 31'h70000000              /*0xE0000000*/ /*System Generator Bank Selection Address*/
`define SYSGEN_STEP_CLOCK_ADDRESS 31'h70000001        /*0xE0000002*/ /*System Generator Step Clock Address*/
`define SYSGEN_MIN_ADDRESS 30'h38000001               /*0xE0000004*/ /*System Generator Databus Start Address*/
`define SYSGEN_MAX_ADDRESS 30'h39000000               /*0xE4000003*/ /*System Generator Databus Max Address*/
`define SYSGEN_BASE_ADDRESS 32'h38000001              /*0xE0000004*/ /*System Generator Base Address*/
`define VFDCM_BASE_ADDRESS 24'hE50000                 /*0xE5000000*/ /*Variable Frequency DCM Base Address*/
`define VFDCM_STATUS_CONTROL_ADDRESS 31'h72800080     /*0xE5000100*/ /*Variable Frequency DCM Control/Status Address*/
`define VFDCM_RESET_PASSWORD 16'hD00F                                /*Variable Frequency DCM Reset Password*/
`define VFDCM_ENABLE_PASSWORD 16'hDA00                               /*Variable Frequency DCM Enable Password*/
`define VFDCM_CLEAR_PASSWORD 16'h0000                                /*Variable Frequency DCM Global Clear*/


//-------------------------General Purpose IO----------------------------
`define GPIO_SETUP 31'h7FFF8000                       /*0xFFFF0000*/ /*GPIO Setup Register [Word Addressing]*/
`define GPIO_RAW   31'h7FFF8001                       /*0xFFFF0002*/ /*GPIO Raw Interface [Word Addressing]*/

//------------------------IO Address Bus Width---------------------------
                                                                     /*The number of bytes accessable by the IO Address Bus is 2^(PCMCIA_ADD_LINES)*/
`define PCMCIA_ADR_LINES 8                                           /*Number of address lines*/
//------------------Tuple and Configuration Registers--------------------
`define COA1_ADDRESS 10'h100                          /*0x200*/      /*This is the base address for the configuration option registers as defined in the TPCC_RADR field of the configuration tuple [Word Addressing]*/
                                                                     /*Configuration option registers (COA) start here*/                                               
`define COA2_ADDRESS 10'h138                          /*0x270*/      /*This is the base address for the configuration option registers as defined in the TPCC_RADR field of the configuration tuple [Word Addressing]*/
                                                                     /*Configuration option registers (COA) start here*/
                                                      
//------------------Memory Address Extension Module----------------------
`define IO_ADDRESS_EXTENSION_1 `PCMCIA_ADR_LINES 'h02 /*0x004*/      /*Address Extension Register A[26:11] (Located in IO Space) [Word Addressing]*/
`define IO_ADDRESS_EXTENSION_2 `PCMCIA_ADR_LINES 'h03 /*0x006*/      /*Address Extension Register A[31:27] (Located in IO Space) [Word Addressing]*/

`define ATTRIB_ADDRESS_EXTENSION_1 10'h10B            /*0x216*/      /*Address Extension Register A[18:11] (Located in Attribute Memory) [8 Bit Even Accesses]*/
`define ATTRIB_ADDRESS_EXTENSION_2 10'h10C            /*0x218*/      /*Address Extension Register A[26:19] (Located in Attribute Memory) [8 Bit Even Accesses]*/
`define ATTRIB_ADDRESS_EXTENSION_3 10'h10D            /*0x21A*/      /*Address Extension Register A[31:27] (Located in Attribute Memory) [8 Bit Even Accesses]*/

//--------------------JTAG Parallel Port Emulator------------------------
`define LPT_DATA_ADDRESS 2'h0                         /*0x000*/      /*LPT IO Base Address         [Byte Addressing]*/
`define LPT_STATUS_ADDRESS 2'h1                       /*0x001*/      /*LPT IO Base Address + 1     [Byte Addressing]*/
`define LPT_CTRL_ADDRESS 2'h2                         /*0x002*/      /*LPT IO Base Address + 2     [Byte Addressing]*/

//-------------------------Status and Reset------------------------------
`define STATUS_ADDRESS `PCMCIA_ADR_LINES'h07          /*0x00E*/      /*Writing the FLASH_RESET_PASSWORD to this address does a hardware reset to the card [Word Addressing]*/
`define STATUS_FLASH_READY                            16'h1          /*Flash READY/BUSY Status*/
`define STATUS_DCMS_LOCKED                            16'h2          /*DCM Locked Snoop*/
`define STATUS_BACKPLANE_DETECTED                     16'h4          /*Backplane Detected or Not*/
`define PICOPORT_RESET_PPC                            `STATUS_ADDRESS/*Give the reset port a more sensible name*/
`define FLASH_RESET_PASSWORD                          16'hDEAF       /*This is password to execute a flash rom reset*/
`define MAGIC_NUM_ADDR                                `PCMCIA_ADR_LINES 'h06 /*0x0C*/
`define PICO_MAGIC_NUM                                16'h5397

//-------------------CPLD Controller (TurboLoader)-----------------------
`define CPLD_CONTROLLER_RELOAD_PASSWORD 8'hAD                        /*CPLD Reload Password*/
`define CPLD_CONTROLLER_RELOAD_ADDRESS 10'h208        /*0x410*/      /*CPLD Reload Address [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_LLSB_ADDRESS 10'h20A /*0x414*/      /*CPLD Peekaboo LLSBs [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_LMSB_ADDRESS 10'h20B /*0x416*/      /*CPLD Peekaboo LMSBs [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_MLSB_ADDRESS 10'h20C /*0x418*/      /*CPLD Peekaboo LLSBs [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_MMSB_ADDRESS 10'h20D /*0x41A*/      /*CPLD Peekaboo LMSBs [Word Addressing]*/


//--------------------------DCM Utilization------------------------------
//`define DISABLE_DCM1                                               /*Each DCM that is not used must be disabled*/
//`define DISABLE_DCM2                                               /*One DCM is used by the compact flash decoder*/
`define DISABLE_DCM3                                                 /*Commenting these out when a DCM is not in use voids warranty*/
`define DISABLE_DCM4                                   
`ifdef IS_LX25                                                      /*There are only 4 DCMs on the E-12 EP*/
   `define DISABLE_DCM5
   `define DISABLE_DCM6
   `define DISABLE_DCM7
   `define DISABLE_DCM8                                              /*This should be the last DCM commented out*/
`endif

//---------------------------------Default address range definitions (DH)
`define OPB_KEYHOLE_BASEADDR   32'h70000000      //OPB keyhole base address
`define OPB_KEYHOLE_HIGHADDR   32'h7000001f      //OPB keyhole high address
`define OPB_CTRL_BASEADDR      32'h70000020      //OPB control base address
`define OPB_CTRL_HIGHADDR      32'h7000002f      //OPB control high address
`define OPB_PEEKABOO           32'h70000024      //R: peekaboo port from CPLD containing last address loaded
`define OPB_REBOOT             32'h70000024      //W: write to this port arms reload logic
`define OPB_FLASH_BASEADDR     32'h60000000      //OPB flash base address
`define OPB_FLASH_HIGHADDR     32'h67ffffff      //OPB flash high address
`define OPB_BASEADDR           32'h6fffff00      //OPB base address
`define OPB_HIGHADDR           32'h6fffffff      //OPB high address
`define OPB_BUSBRIDGE_BASEADDR 32'h60000000      //OPB flash base address
`define OPB_BUSBRIDGE_HIGHADDR 32'h67ffffff      //OPB flash high address
`define OPB_BUSBRIDGE_WINDOW_REG_ADDR  32'h70000030
`define OPB_BUSBRIDGE_ACCESS_TYPE_ADDR 32'h70000034
`define OPB_DATALOCK_BASEADDR  32'h70000050      //OPB DataLock base address
`define OPB_DATALOCK_HIGHADDR  32'h7000005f      //OPB DataLock high address

//---------------------------------PPC Control Registers
                                                      //The PPC reset addr is now the same as the flash reset addr - RESET_ADDRESS
`define PPC_RST_PASSWORD     8'hDF                    //System reset password = DF
`define PCMCIA_KEYHOLE_MISC  8'h0E                    //misc    register for keyhole debugging (read  only).
//------- PPC side -------- PPC->PC keyhole Registers
`define OPB_PPC2PC_CMND    (`OPB_KEYHOLE_BASEADDR+0)  //command register for ppc2pc_fifo (write only) = 0x70000000.
`define OPB_PPC2PC_DATA    (`OPB_KEYHOLE_BASEADDR+4)  //data    register for ppc2pc_fifo (write only) = 0x70000004.
`define OPB_PPC2PC_STAT    (`OPB_KEYHOLE_BASEADDR+8)  //status  register for ppc2pc fifo (read  only) = 0x70000008.
`define OPB_KEYHOLE_MISC   (`OPB_KEYHOLE_BASEADDR+12) //misc    register for keyhole debugging (read  only).
//------------------------- PC->PPC keyhole Registers
`define OPB_PC2PPC_CMND    (`OPB_KEYHOLE_BASEADDR+16) //command register for pc2ppc_fifo (read  only) = 0x70000010.
`define OPB_PC2PPC_DATA    (`OPB_KEYHOLE_BASEADDR+20) //data    register for pc2ppc_fifo (read  only) = 0x70000014.
`define OPB_PC2PPC_STAT    (`OPB_KEYHOLE_BASEADDR+24) //status  register for pc2ppc fifo (read  only) = 0x70000018.

//------- PCMCIA side ----- PPC->PC keyhole Registers
`define PCMCIA_PPC2PC_CMND   8'h14                    //command register for ppc2pc_fifo (read  only).
`define PCMCIA_PPC2PC_STAT   8'h54                    //status  register for ppc2pc fifo (read  only).
`define PCMCIA_PPC2PC_DATA   8'h1c                    //data    register for ppc2pc_fifo (read  only).
//------------------------- PC->PPC keyhole Registers
`define PCMCIA_PC2PPC_CMND   8'h24                    //command register for pc2ppc_fifo (write only).
`define PCMCIA_PC2PPC_STAT   8'h5C                    //status  register for pc2ppc fifo (read  only).
`define PCMCIA_PC2PPC_DATA   8'h2C                    //data    register for pc2ppc_fifo (write only).

//--------------------------Capabilities (read by PPC) -------------------------------------------------------------
`define OPB_CAPABILITIES (`OPB_KEYHOLE_BASEADDR+44) //capabilities register for ppc = 0x7000002C.

//--------------------------Interrupt remapping --------------------------------------------------------------------
`define OPB_INTERRUPT_MAP (32'h70010000)            //used to provide instructions to interrupt processing

//--------------------------Sample code: Counter -------------------------------------------------------------------
`define PCMCIA_SAMPLE_DATA   32'hFC
`define OPB_SAMPLE_DATA      32'h70000FC0

//--------Defines associated with channel allocation -----------------------------------------------
`define BM_CHANNEL_BASE         32'h10100000       //address of BM devices is 0x1010,0000 thru 0x7FFF,FFFF
`define BM_CHANNEL_SIZE         32'h100000         //size of each device is one megabyte
`define BM_MAX_CHANNELS         1791               //number of one meg channels that fit in the above address space.
`define BM_CHANNEL_STATUS_BASE  32'h10000010       //channel #1 statuses start at this address.
`define BM_CHANNEL_STATUS_SIZE  32'h10             //each channel has space for 4 * 32bit registers.
`define BM_ADDR_FROM_CHANNEL(channel)   (`BM_CHANNEL_BASE         + (channel-1) * `BM_CHANNEL_SIZE)
`define BM_STATUS_FROM_CHANNEL(channel) (`BM_CHANNEL_STATUS_BASE  + (channel-1) * `BM_CHANNEL_STATUS_SIZE)
`define BM_READ_STATUS_SIGNATURE  6'h26              //signature of BM read  status register.
`define BM_WRITE_STATUS_SIGNATURE 6'h22              //signature of BM write status register.

//--------Defines associated with stream allocation ------------------------------------------------
// (note that since streams are an of extension of channels, they use the same addresses.)
`define PICO_STREAM_BASE        (`BM_CHANNEL_BASE)
`define PICO_STREAM_SIZE        (`BM_CHANNEL_SIZE)
`define PICO_MAX_STREAMS        (`BM_MAX_CHANNELS)
`define PICO_STREAM_STATUS_BASE (`BM_CHANNEL_STATUS_BASE)
`define PICO_STREAM_STATUS_SIZE (`BM_CHANNEL_STATUS_SIZE)

//-------------------------- DataLock Module -----------------------------------------------------------------------
`define PCMCIA_PPC2PC_LOCK_DATA 8'hA4
`define PCMCIA_PC2PPC_LOCK_DATA 8'hAC
`define OPB_PPC2PC_LOCK_DATA    32'h70000050
`define OPB_PC2PPC_LOCK_DATA    32'h70000054

`endif
